Arteris IP Ncore Cache Coherent Interconnect
The Coherency Company.
Overview
Arteris Ncore is a cache coherent Network-on-Chip (NoC) interconnect IP that enables the seamless integration of multiple processor clusters and other coherent agents in a System-on-Chip. It provides high-bandwidth, low-latency communication while ensuring system-wide data coherency, which is critical for heterogeneous compute systems, automotive ADAS, and data center applications. Its configurability allows architects to optimize the interconnect for their specific performance, power, and area requirements.
✨ Key Features
- Scalable cache coherency for heterogeneous systems
- Support for Arm AMBA CHI and AXI protocols
- Highly configurable to optimize PPA (Power, Performance, Area)
- Advanced debugging and performance analysis tools
- Functional safety features for automotive applications (ISO 26262)
🎯 Key Differentiators
- Processor-agnostic, supporting both Arm and RISC-V
- Highly flexible and configurable architecture
- Advanced functional safety features for automotive
Unique Value: Provides a flexible, high-performance, and functionally safe interconnect solution that simplifies the design of complex, heterogeneous, multi-core SoCs.
🎯 Use Cases (5)
✅ Best For
- Connecting multiple Arm Cortex-A clusters in a mobile SoC
- Providing coherent communication between CPUs and AI accelerators in an automotive chip
- Building scalable, multi-chiplet systems using coherent links
💡 Check With Vendor
Verify these considerations match your specific requirements:
- Simple SoCs without multiple coherent processor clusters
- Designs that only require a basic non-coherent bus
🏆 Alternatives
Offers greater flexibility and independence compared to processor-vendor-specific interconnects like Arm's, allowing for true heterogeneous system design.
💻 Platforms
✅ Offline Mode Available
🔌 Integrations
🛟 Support Options
- ✓ Email Support
- ✓ Phone Support
- ✓ Dedicated Support (Licensing tier)
🔒 Compliance & Security
💰 Pricing
Free tier: N/A
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