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🔧 Yosys

Yosys

A framework for Verilog RTL synthesis.

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Overview

Yosys is a versatile, open-source framework for Verilog RTL synthesis. It forms the core of many open-source FPGA and ASIC flows. Yosys can read Verilog and SystemVerilog designs, perform synthesis and technology mapping, and write out results in various formats, including structural Verilog, BLIF, EDIF, and JSON. It is highly extensible and scriptable.

✨ Key Features

  • Verilog-2005 and SystemVerilog (synthesizable subset) support
  • Extensible framework with a rich scripting interface (Tcl)
  • Support for formal verification (e.g., equivalence checking)
  • Technology mapping for various FPGA architectures (Lattice, Xilinx, etc.)
  • ASIC synthesis capabilities (with OpenROAD/OpenLane)
  • Free and open source

🎯 Key Differentiators

  • Completely open source and highly extensible
  • Vendor-neutral, supporting multiple FPGA and ASIC targets
  • Strong capabilities for formal verification

Unique Value: Provides a free, open, and extensible synthesis framework that gives designers complete control and transparency over the synthesis process.

🎯 Use Cases (5)

Core of open-source FPGA toolchains (e.g., for Lattice iCE40/ECP5) Formal verification and equivalence checking ASIC synthesis in open-source flows Technology exploration and research Custom synthesis and design analysis tasks

✅ Best For

  • Complete open-source toolchain for Lattice iCE40 FPGAs
  • Synthesis component of the OpenLane ASIC toolchain
  • Used in academic research for novel synthesis algorithms

💡 Check With Vendor

Verify these considerations match your specific requirements:

  • Users who need a GUI-based, push-button synthesis solution
  • Designs requiring the absolute highest performance on the latest, largest FPGAs (vendor tools are often better optimized)

🏆 Alternatives

Synopsys Synplify Pro AMD Vivado Synthesis Intel Quartus Prime Synthesis

Unlike the 'black box' nature of proprietary synthesis tools, Yosys is fully transparent, allowing for inspection, customization, and extension, which is invaluable for research, security, and custom flows.

💻 Platforms

Desktop (Linux, Windows via WSL/MSYS2, macOS)

✅ Offline Mode Available

🔌 Integrations

nextpnr (place and route) GHDL (for VHDL support via plugin) Verilator (for simulation) OpenROAD Project (for ASIC implementation)

💰 Pricing

Contact for pricing
Free Tier Available

Free tier: Yosys is completely free and open source.

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